DDR4 Sdram – Initialization, Training and Calibration (systemverilog.io)
31 points by todsacerdoti 3 days ago
MisterTea an hour ago
From my understanding, memory training is/was a closely held secret of memory makers and EDA IP houses who sold memory controller IP to all the chip vendors. This in turn makes fully open motherboard firmware almost impossible as no one can write code for memory training to bring up the chip. That piece of code has to be loaded as a blob - if you can get the blob.
brcmthrowaway 27 minutes ago
Why do we need training?
nvme0n1p1 20 minutes ago
It's in the link. https://www.systemverilog.io/design/ddr4-initialization-and-...