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As it can be seen from the photos, horizontally the features are much bigger than 5 nm.

For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.

The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.

The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer, but that does not matter directly for the circuit density.

The supposed node size refers to horizontal dimensions, not to vertical dimensions.

Vertical dimensions of around 1 nanometer or less could be achieved already many decades ago, because they depend on growth speed and on time, not on lithography, like the horizontal dimensions.

The industry should have stopped decades ago to talk about the "size" but they should have characterized a CMOS process by its density, e.g. in logic gates per square mm.

However, an actual concrete number would be disliked by marketing, because they could no longer claim that their "1 nm" process is better than the "2 nm" process of another vendor, if their density is not really better.

Unlike marketing terms, "nm density" is actually useful measure.

It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

It's been decades since published node sizes had any connection to actual feature size. Sadly this is just how it works in the semiconductor industry now.

My read on it was that they are trying to imply a transistor density (in a 2D plane sense) that is comparable to a 1nm process? But they achieve that through stacking (3D, not 2D) since the features aren't actually anywhere near 1nm?

What industry doesn't have a few too many marketers? Take everything with a grain of salt.

yeah, where on the pictures is the 0.7nm feature? The linespacing is around 5nm. Is it the white line which is 0.7nm?

I believe it could be a stepping stone to significantly higher density in the future.

Better metrics are transistors/mm^2, performance/watt, and raw performance, since at this point "nm" is fluff and easily game-able.

Different companies measure it differently too. This was a while ago, but I remember reading that Intel 10nm was more or less close to TSMC 7nm. I'm sure this is still true to varying degrees.

only a matter of time before some marketer figures out they can get promoted by branding a generation of chips 0nm

On the otherhand, no investor really cares what it's called, they just need to know it's next gen.

> Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.

We care about PPA (power, performance, area) and not how large or not-large features actually are. Comparing gate lengths between a 1980s planar transistor and a 2010s 3D FinFET or GAA transistor is obviously nonsense, the relatively aligned node names of the industry actually do make sense as a shortcut here.

Generations.

Gen Alpha were born since the naming became detached from actual physical size. And parts of Gen Z (before) and Gen Beta (after).

Hi Dr. Cutress! I loved reading your deep dives on Anand, they're what got me interested in semiconductors. Hope you're well <3

weird q: the photo shows a wafer with partial chips rendered on the edges?

It was 15 years ago. Whole management got replaced, they are quite ambitious. Let's see if how this works out now.

Most of their fabs were divested to GlobalFoundries, but they still have pretty significant fab capability and capacity- I suspect at least partly to have a us-based chip-making for military ("Trusted Foundry").

The labs might not be that different from consulting, the NYT reporting on this notes they run R&D labs so they can license the tech they develop to people who actually make chips.

IBM has been the company with the most patent registrations in the US for I think 29 of the last 30 years. They're one of the largest industrial research organizations in the world. They're doing more hard science research than almost anyone else.

Yes, and we're already there. We've been there for quite a while, in fact.

Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know. Electrons just aren't physical objects at this scale, you can't simply exclude them from any given volume of space. The electron wave function will simply just appear wherever it wants (within the electron probability cloud). The only way to stop it is to make your insulating junction thicker than the probability cloud.

https://en.wikipedia.org/wiki/There%27s_Plenty_of_Room_at_th...

https://en.wikipedia.org/wiki/Landauer%27s_principle

I mean, you can't get smaller than an atom, there is some amount of plausibility of using individual atoms as at least the occasional computing element.

Beyond that, engineering a quark-gluon plasma as a processor? I'd watch that Star Trek episode. (we might fantasize about stuff like that but we're roughly monkeys smashing rocks together in a cave vs. building an iPhone sort of gap away from that kind of thing unless somebody has a really good idea)

> Do they license this out to fabs?

Broadly speaking yes, this is the business model. IBM has been at this for many years with technology transfers, licensing agreements, support and other arrangements. Rapidus, Samsung, GlobalFoundries, ST, SMIC, AMD, etc. have all used IBM R&D work at various times for various nodes and products.

The cutting edge of semiconductors is a writhing mass of copulating tapeworms, and IBM lives deep inside that ball. For IBM, what this means is that when you buy one of the ASML machines to make products with this process, you'll pay IBM for the knowledge and support to actually get it working, or give them a cut, or something else, TBD, as circumstances warrant.

They licensed 2 nm to Rapidus so yes.

I’m sure they will license it. It’s better for them if everyone in the industry can innovate on everything around it. All the process tech companies will make it more cost effective, for instance, which helps IBM as well.

boost sales for their systems division, POWER CPUs, mainframes, maybe Quantum stuff

Sit on a patent and try to scrape earnings from others, maybe? That is, license or litigate.

Approximately everyone (at least in the F500) outside of Big Tech uses them. For example, Costco's entire inventory management system runs on IBM i (so, POWER). You can see the classic terminal look around the store. Banks run a TON of z and i. You'll never see them because they're essentially always in data centers, but I guarantee you interact with them even if it's very non-obvious because there's 50 microservices between the UI and the actual system of record.

Ericsson used a lot of power chips in their telecom hardware 10 years ago at least, haven't worked with their stuff since then so I haven't kept up.

Their line of POWER chips are used in their mainframes

The product here is the research and licensing the tech.

usgov

> remember the "teleportation" ads years ago

Never heard of this, care to elaborate?

Maybe it is done to pump their stock with low effort? It seems that way for many companies.

I know what it means. Something isn't automatically bullshit because it's outside your field of expertise.

Cymer builds the EUV light source, but the biggest enabler for High NA EUV is using anamorphic optics (ie asymmetric horizontal and vertical magnification) from Zeiss: https://www.asml.com/en/news/stories/2024/5-things-high-na-e...

Correct

The industry does use a collection of more practical measurements, like transistor density. Marketing pieces for the news tend to use this kind of jargon precisely because it can be fudged & it sounds like it means something else than it really does to the average person. It's also simple enough to avoid needing to really explain what kinds of numbers are impressive etc, everyone just knows less than 1 nm is tiny and they've heard X nm for decades to compare to at this point.

>These are not, in fact, physically sub 1 nm, despite the bombastic claims.

Why? What's their real size?

Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.

The marketing nm better represent the density and performance of the transistors than the actual feature size, especially in this case.

So the title should be corrected. The did not debut sub nm chips at all.

Well Watson went from a product, to product line branding. Then changed to Watsonx.

Doing a search on that there are loads of news articles.

They have small scale fabrication capabilities or they wouldn’t be able to validate the technology enough to sell it.

Yes, shortly followed by negative space chips

Isnt that quantum computing?

It'll be a brave man who takes on the IBM legal department over terminology in widespread use.

My understanding is they are largely an IP business. That said this release mentioned an ASML machine on prem, so?

IBM's contributions to computing hardware and software are incalculable.

So many breakthroughs in hard drives, chips, transistor density, and other aspects of computing have come out of their labs.

Great to see them continuing to innovate.

But, yeah, usually they partner and license. Over the years, they've spun off more and more of their hardware businesses.

I believe that IBM makes the chips for their Z Series mainframes. I mean, that's low volume production, but they need small feature size.

There are 3 orders of magnitude between nano (^-9) and pico (^-12). An Angstrom is ^-10m.

Because 1 angstrom equals 10⁻¹⁰ meters and 1 picometer equals 10⁻¹² meters, the relationship is:

1 Å = 100 pm. 1 pm = 0.01 Å.

1 picometer = 0.001 nanometers, 0.01 angstrom

1 angstrom = 0.1 nanometers, 100 picometers

1 nanometer = 10 angstroms, 1000 picometers